Intel says it has already passed a million High-NA EUV wafers – more than the rest of the industry combined

The recent SPIE Photomask Technology and EUV Lithography conference in Monterey, California, served as the stage for a landmark announcement in the semiconductor industry. Intel Foundry, in collaboration with ASML, confirmed that they have successfully processed over one million 300mm silicon wafers using High Numerical Aperture (High NA) Extreme Ultraviolet (EUV) lithography systems. This achievement is not merely a quantitative record; it represents a fundamental shift in the feasibility of sub-nanometer chip fabrication, cementing Intel’s commitment to its aggressive foundry roadmap despite the turbulent financial and operational challenges the company has navigated over the past two years.

A Chronology of High NA Adoption

The journey toward this one-million-wafer milestone began years before the hardware even reached the factory floor. The development of High NA EUV technology was born out of the necessity to continue scaling Moore’s Law. As traditional EUV (0.33 NA) systems reached their physical limits in patterning the increasingly dense transistors required for modern AI accelerators and high-performance CPUs, the industry looked to High NA (0.55 NA) as the next logical evolution.

Intel was the first customer to receive the EXE:5000 system, ASML’s pilot High NA tool, in late 2023. The installation process at Intel’s D1X facility in Oregon was a logistical feat, requiring specialized logistics to transport massive machine components. By early 2024, the machines were operational, and the focus shifted from installation to calibration and yield optimization. Throughout 2024 and 2025, Intel integrated these machines into its research and development pipeline, eventually moving toward the production of its Panther Lake (Core Ultra Series 3) architecture. Reaching one million wafers indicates that the technology has transitioned from an experimental pilot phase to a functional manufacturing capability.

Understanding the Data: Contextualizing the Million-Wafer Figure

The figure of one million wafers, while impressive, requires careful interpretation. According to the joint statement from the two companies, this total is an aggregate of several distinct manufacturing stages: R&D experimentation, the rigorous tool certification process, and the early volume production of the Core Ultra Series 3 line.

It is critical to note that "one million wafers" does not imply one million finished, yield-ready commercial chips. Instead, it reflects the total number of wafers that have passed through the High NA exposure process. This includes test wafers used to calibrate the complex optical alignment of the 0.55 NA lenses—a system that utilizes an entirely new anamorphic lens design to project patterns onto silicon.

To put this in a broader industry context, ASML’s leadership recently disclosed that their fleet of EXE systems globally has exposed approximately 1.35 million wafers across all customers. This places Intel’s contributions at roughly 74% of the global total for High NA exposure. This disparity highlights that while other major foundry players like TSMC, Samsung, and SK Hynix are testing and evaluating High NA technology, Intel has essentially adopted a "first-mover" strategy, bearing the brunt of the initial technical hurdles in exchange for early mastery of the process.

The Financial and Strategic Stakes

Intel’s aggressive investment in High NA EUV, where each machine commands a price tag upwards of $350 million, is part of a broader "bet the farm" strategy. Following a period where the company struggled to maintain its dominance in the face of rising competition from Nvidia in the AI space and TSMC in contract manufacturing, the foundry business has become the cornerstone of its recovery plan.

The financial markets have reacted with cautious optimism. Intel’s stock price has seen a significant recovery of roughly 155% year-to-date, fueled by the company’s efforts to open its fabs to external clients through the Intel Foundry model. The fact that the US government—through the CHIPS Act—and various strategic partners have taken a vested interest in the company’s success underscores the geopolitical importance of this manufacturing capability. By becoming the only foundry with a proven track record of using High NA tools for shipping products, Intel is positioning itself to be the primary domestic manufacturer for the next generation of AI-heavy computing hardware.

Technical Hurdles and the Path Forward

The transition to High NA EUV is not without its detractors. Critics often point to the astronomical cost of the machines and the complexity of the photoresist materials required to work with the higher energy beams. High NA systems utilize a 0.55 NA lens, which provides superior resolution compared to the 0.33 NA of standard EUV. This allows for smaller critical dimensions, effectively allowing designers to pack more transistors into a smaller surface area without the need for multi-patterning—a process that is both costly and prone to alignment errors.

However, the "first-mover" advantage carries inherent risks. Early adopters often face lower yields and higher operational overhead as they refine the calibration of the machines. Intel’s one-million-wafer milestone suggests that these early yield issues are being systematically addressed. By running millions of wafers through the system, the company is generating the massive data sets required to train AI-driven lithography control software, further optimizing the process for future iterations.

Industry Implications and the Competitive Landscape

The competitive landscape for High NA lithography remains polarized. While Intel has moved full speed ahead, others are taking a more measured approach. TSMC, for instance, has publicly stated that it does not intend to move to high-volume manufacturing with High NA EUV until at least 2030, preferring to maximize the efficiency of its existing 0.33 NA infrastructure.

This divergence in strategy creates two distinct paths for the semiconductor industry:

1. The Optimization Path: Players like TSMC are focusing on refining existing EUV technology to its absolute limit, potentially keeping costs lower for their customers in the short term.
2. The Innovation Path: Intel is betting that the physical limitations of current EUV will create a "hard wall," and that by mastering High NA now, they will have a significant performance and density advantage when the market shifts toward 2nm and sub-2nm nodes.

For the broader tech ecosystem, the implications are profound. If Intel can successfully scale this technology, it could potentially reclaim the process node lead, allowing it to produce chips that are smaller, faster, and more power-efficient than those manufactured using legacy EUV techniques. This would have a direct impact on the performance of future data centers, high-end consumer laptops, and autonomous driving systems.

Official Responses and Future Outlook

Neither Intel nor ASML has provided a granular breakdown of how many of the one million wafers were dedicated to specific product lines, such as the Panther Lake chips. However, the tone from both companies is one of validation. ASML’s Greet Storms, who manages the High NA product line, noted that the collective exposure numbers across all customers demonstrate that High NA is no longer a "lab experiment."

For Intel, the milestone is a necessary narrative shift. Having been labeled by some analysts as an "also-ran" in the AI race, the company is using this technical achievement to signal that its foundry division is operational and, more importantly, technically superior in its lithography capabilities.

As we look toward the next three years, the industry will be watching to see if Intel can maintain this pace. The transition from R&D to high-volume manufacturing is often where the most significant failures occur. However, with ten systems currently live across the industry and more being installed, the High NA era has officially begun. Intel’s head start, represented by its majority share of wafer exposure, suggests that while the race to the next node is far from over, they have successfully secured a critical technical advantage that will be difficult for competitors to replicate without significant investment and time.

The success of the High NA program will ultimately be measured not by the number of wafers exposed, but by the performance and market adoption of the chips that emerge from these machines. If Intel’s Panther Lake and future architectures can leverage this lithography to deliver superior performance per watt, the "million wafer" milestone will be remembered as the moment the industry moved past the limits of traditional EUV and into a new era of silicon density.